Synopsys' ESP Full-Custom Memory Verification Enables Artisan to Achieve 5X Faster Time to Results
Unique Symbolic Simulation Speeds Verification for Artisan's New Low-Power, High-Density Metro Platform Memories
MOUNTAIN VIEW, Calif., Dec. 21 /PRNewswire-FirstCall/ -- Synopsys, Inc. (NASDAQ: SNPS), a world leader in semiconductor design software, announced that Artisan Components, Inc., has standardized on Synopsys' ESP full-custom memory equivalency checker for its new low-power, high-density Metro(TM) Platform memories. ESP's unique symbolic simulation technology enabled Artisan to verify its memory generators, while realizing a 5X reduction in time-to-results as compared to verification methods that rely on traditional simulation only.
"ESP -- our longstanding choice for memory verification -- gives us fast, comprehensive equivalency checking that enables us to cut our time-to-results from days to hours," said Dhrumil Gandhi, senior vice president of product technology at Artisan. "In order to support leading-edge low-power design techniques, Artisan's Metro memories are significantly more complex. Synopsys' ESP verification solution plays a major role in helping us meet our customers' first-pass silicon requirements."
ESP is a fast, comprehensive memory equivalency checker that addresses the gap in full-custom verification by thoroughly and quickly comparing a Verilog simulation model directly against the corresponding HSPICE netlist. Its patented application of symbolic simulation techniques and formal proof engines removes the RTL restrictions and circuit limitations placed on design teams by traditional logic abstraction methods while its proprietary hierarchical compression technique delivers the increased capacity demanded by today's memory systems. ESP is ideally suited for verifying embedded memories in system-on-chip (SoC) designs.
"Artisan's standardization on ESP further validates our continued investment in a comprehensive range of industry-leading verification technologies that cover the RTL, gate and transistor-level space," said Bijan Kiani, vice president of Marketing at Synopsys. "ESP, coupled with our Formality(R) equivalence checking software, delivers the industry's only functional equivalence checking solution capable of verifying complex SoCs that contain full-custom memories, cell-based logic, and third-party IP blocks."
About Synopsys
Synopsys, Inc. is a world leader in electronic design automation (EDA) software for semiconductor design. The company delivers technology-leading semiconductor design and verification platforms and IC manufacturing software products to the global electronics market, enabling the development and production of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California, and has more than 60 offices located throughout North America, Europe, Japan and Asia. Visit Synopsys online at http://www.synopsys.com/ .
NOTE: Synopsys is a registered trademark of Synopsys, Inc., and Galaxy is a trademark of Synopsys. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.
CONTACT: Yvette Huygen of Synopsys, Inc., +1-650-584-4547, or
yvetteh@synopsys.com; or Sarah Seifert of Edelman Public Relations,
+1-650-429-2776, or Sarah.seifert@edelman.com, for Synopsys, Inc.
Web site: http://www.synopsys.com/
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